AMD Unveils First 2-Nanometer Wafer Powered by TSMC Technology

AMD has provided a significant glimpse into its upcoming generation of server processors, codenamed Venice, which will utilize TSMC's cutting-edge 2-nanometer (N2) manufacturing technology. The company has confirmed that the initial test wafers featuring these advanced chips have already been produced.

This new Epyc processor generation is set to be the first to incorporate TSMC's 2-nanometer technology, designed specifically for high-performance computing (HPC) applications. However, the official market launch is still some time away, with an anticipated reveal in 2026, likely in the latter half of the year.

Notably, TSMC's shift to N2 technology marks a transition from the well-established FinFET transistor architecture to a more advanced Gate-All-Around Transistor (GAAFET) design, which TSMC refers to as Nanosheets.

While AMD has not disclosed extensive details about the Venice processors, it is rumored that the flagship model may feature up to 256 Zen-6 cores. These cores would be distributed across eight compute chiplets, each containing 32 cores built using the 2-nanometer technology. The information regarding the chip configuration has emerged from the YouTube channel 'Moore's Law is Dead,' although its reliability has been variable. It is expected that the I/O die, which includes memory controllers and PCI-Express interfaces, will be fabricated separately, likely using older manufacturing processes.

Furthermore, AMD appears poised to introduce a new compute chiplet for desktop PCs for the first time since the launch of the Zen architecture. This desktop chiplet is anticipated to include 12 Zen-6 cores and will also be manufactured at TSMC using the 2-nanometer process. New Ryzen high-end models could potentially feature 24 cores along with additional efficiency cores integrated into the I/O die.

In addition to its collaboration with TSMC, AMD has highlighted its commitment to domestic production within the United States. The company, in conjunction with TSMC, has successfully validated the first Epyc 9005 chiplets fabricated using 4-nanometer technology at their new semiconductor facility in Arizona. This development suggests that U.S. customers will soon have access to Epyc 9005 processors that are partially produced domestically, specifically aimed at high-performance computing applications.